Navitas UHV-TO-247-4-ISO Package Unveiled for SiC MOSFETs

The Navitas UHV-TO-247-4-ISO package has officially launched, marking a significant milestone in high-power discrete semiconductor packaging. Developed by Navitas Semiconductor, a prominent player in next-generation gallium nitride (GaN) and silicon carbide (SiC) power technologies, this innovative through-hole package delivers power-module-class performance within a highly compact discrete footprint.

Specifically engineered for high-voltage applications spanning 1200 V to 3300 V, the new packaging technology supports the company’s GeneSiC SiC MOSFET portfolio. By mitigating traditional isolation bottlenecks, this architecture paves the way for direct-cooled thermal management systems across grid infrastructures, renewable energy, and AI data centers.

The Challenge of High-Power Thermal Isolation

In industrial power electronics design, managing high voltages while maintaining efficient thermal paths has long been a complex trade-off. Standard through-hole packages like the traditional TO-247 typically require external thermal interface materials (TIMs) and ceramic insulators to isolate the tab from the heatsink.

However, these external layers introduce significant thermal resistance ($R_{TH}$), limiting overall power density and system reliability. Furthermore, external insulation materials add complexity to automated manufacturing assemblies and increase vulnerability to mechanical stress over extended operational lifetimes.

Key Technical Specifications of the UHV-TO-247-4-ISO

The Navitas UHV-TO-247-4-ISO package addresses these integration challenges directly at the component level. By embedding high-voltage isolation internally, the discrete device eliminates system-level insulation steps entirely.

• Integrated Isolation Voltage: Exceeds 6000 V, eliminating the need for external ceramic sheets or isolation barriers.
• Creepage Distance: Features a pin-to-pin creepage distance of over 12 mm, ensuring compliance with strict high-voltage safety standards.
• Substrate Technology: Utilizes a high-performance Aluminum Nitride (AlN) substrate coupled with active metal brazing (AMB) technology.
• Form Factor Compatibility: Fully compatible with industry-standard TO-247-4 form factors and lead geometries, allowing drop-in integration without extensive PCB redesign.

Direct-Cooled Thermal Management and System Benefits

Integrating an isolated substrate directly within the discrete device package fundamentally changes the thermal stackups used by hardware design engineers.

Up to 150% Increase in Power Dissipation

Because the package incorporates a reflow-compatible thermal pad, it can be mounted directly onto liquid- or air-cooled heatsinks. This configuration removes external TIMs from the thermal path, reducing junction-to-heatsink thermal resistance ($R_{TH,J-HS}$) by up to 60%. As a direct consequence, hardware architectures can achieve up to a 150% increase in power dissipation capability, drastically raising power density boundaries.

Mitigating Radiated EMI and Stray Capacitance

High-speed switching in SiC MOSFETs often induces common-mode noise due to parasitic coupling capacitance between the transistor die and the grounded heatsink. The internal AlN substrate structure of the package minimizes this die-to-heatsink stray capacitance compared to external ceramic isolators. This structural optimization suppresses common-mode electrical noise and lowers radiated electromagnetic interference (EMI), minimizing the size, weight, and cost of external EMI filters.

Enhanced Power and Thermal Cycling Reliability

The removal of distinct external material layers with mismatched coefficients of thermal expansion (CTE) enhances mechanical durability. Combining the AMB technology with a robust, reflow-compatible interface ensures the device withstands harsh thermal cycling conditions. This extension of operational lifetime is vital for demanding industrial environments where system maintenance down-time must be minimized.

Broadening the High-Voltage SiC Portfolio

The introduction of the Navitas UHV-TO-247-4-ISO package expands the company’s existing high-performance portfolio, which already features SiCPAK power modules, QDPAK, and TO-247-LP form factors. This new addition focuses explicitly on applications requiring modular performance tiers but preferring discrete assembly cost structures.

According to Paul Wheeler, VP & GM of the SiC Business Unit at Navitas, balancing thermal efficiency with robust isolation remains a fundamental challenge in high-power design. He emphasized that this new packaging solution offers a highly efficient building block that allows system engineers to maximize the performance of GeneSiC SiC MOSFETs in demanding scenarios, including immersion-cooled and liquid-cooled environments.

Target B2B Industrial Applications

The voltage ratings and current capabilities offered by this platform target large-scale electrical infrastructure and industrial automation deployments:

• Grid-Tied Power Conversion Systems (PCS): Enhancing efficiency and reducing structural volume in utility-scale energy storage inverters.
• Solid-State Transformers (SST): Supporting higher power density configurations in localized medium-voltage grid distribution networks.
• Battery Energy Storage Systems (BESS): Streamlining thermal setups in high-capacity commercial and industrial battery storage units.
• Renewable Energy Generation: Improving power conversion reliability and performance in central solar inverters and wind energy systems.
• AI Data Center Power Supplies: Supporting high-efficiency, high-density power distribution units (PDUs) required by modern high-density compute clusters.

Product Line Matrix

The new isolated through-hole package is available across various voltage and on-resistance configurations to meet diverse system architectures:

Industry Availability

Navitas is showcasing the new package variant alongside its specialized direct-cooled heatsink assembly during PCIM Europe 2026 in Nuremberg. Technical representatives will be presenting the hardware ecosystem at Booth #544 in Hall 9. Engineering samples and design-in resources are accessible via formal semiconductor distribution channels.

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